There are many situations in circuit design in which it is desirable to generate clock intervals in a system that occur at a higher rate than the system clock. For example, a computer processor may have a primary clock of 66 MHz while it is desirable to operate internally at 3.3 GHz. To do so, each 66 MHz clock interval must be divided into 50 equal parts, so that the 50 parts thus correspond to a clock of 3.3 GHz.
One way to construct a simple “clock doubler” is to delay a clock signal by one-quarter of the clock period. FIG. 1 shows a 100 MHz sine wave signal 102. Such a signal has a clock period of 10 nanoseconds (ns), so that the first clock cycle shown starts at 0 and ends at 10 ns on the horizontal axis, where another clock cycle begins. As is easily seen, signal 102 also has a zero crossing at 5 ns, since a negative (where the signal is falling) edge falls halfway between the positive (rising) edge of the first clock cycle that begins at 0, and the positive edge of the second cycle that begins at 10 ns. Signal 102 will thus have zero crossings that are regularly spaced every 5 ns. Typically, each zero crossing, whether from a positive or negative edge, may be used as a trigger for circuit components.
As also shown on FIG. 1, if the 100 MHz signal 102 is delayed by 2.5 ns, and the delayed signal 104 overlaid on the original signal, there will be additional zero crossings halfway in between the zero crossings of the original signal, i.e., regularly spaced every 2.5 ns, since every zero crossing in the original signal is replicated 2.5 ns later in the delayed signal. Thus, the original signal is in effect doubled, as there are now regularly spaced zero crossings every 2.5 ns, rather than only every 5 ns as with only the original signal.
However, while it is well known in the prior art how to make such a fixed time delay, a delay of a given period only results in the additional zero crossings being at equal intervals for a clock signal of a single frequency, i.e., a signal in which the delay is one-quarter of the clock period. If the frequency is changed but the delay remains constant, the zero crossings will not be at regular intervals.
This may be seen in FIG. 2, which shows the result of changing the signal frequency from 100 MHz, as in FIG. 1, to a signal 202 of 150 MHz, while keeping the delay at 2.5 ns, resulting in a delayed signal 204. While each signal 202 and 204 has regularly spaced zero crossings, and there are still twice as many zero crossings as with only the original signal 202, the combined zero crossings of both signals are no longer equally spaced. Thus, the delayed signal 204 cannot be used to effectively make a faster clock than that of the original signal 202, since that faster clock will be irregular.
This shows that a fixed time delay will only result in a regular doubling of a clock frequency if the time delay corresponds to one-quarter of the clock period. The failure to obtain equal spacing in the zero crossings in FIG. 2 is due to the fact that the overlaid signal is delayed by a fixed time, which does not correspond to one-quarter of the clock period of the 150 MHz signal, but rather only to one-quarter of the clock period of the 100 MHz signal of FIG. 1. Thus, a different time delay must be selected for each separate frequency.
There are more complicated circuits which will sub-divide a time interval, such as the example above in which a 66 MHz clock interval must be divided into 50 equal parts to obtain a clock of 3.3 GHz. Such circuits are well known, and are commonly referred to as “clock multipliers,” or often “delay locked loops” or “phase locked loops.” A typical example of such a prior art circuit is shown in FIG. 3. A circuit 300 contains controlled delay elements D1 to D8 that are used to sub-divide the time interval of successive clock cycles. The circuit 300 operates to adjust the delay of each individual delay element such that the time interval to the end of the delay line is substantially equal to the clock period.
Such prior art implementations require a controller, in this case the integrator 302 in FIG. 3, and the use of a control feedback loop 304. The controller operates to ensure that the delay intervals are uniform, so that an even division of the clock period results. This is necessary so that no output interval is substantially longer than any other, as would be the case if the output of the delay line were reached before the next clock input arrived.
The feedback loop 304 has associated stability criteria and a finite time interval (the inverse of the loop bandwidth) over which it operates. In order to be usable with different frequencies, the delay elements D1 to D8 themselves are necessarily adjustable, and the adjustability may conflict with the need to be free from the time uncertainty of the output of the delay line relative to its input known as “jitter,” i.e., the fact that the delay will not be precisely the same for each input clock edge.
Other prior art methods of doubling a clock have been tried, for example, sending a clock signal down a delay line, and tapping the signal at a point on the delay line which corresponds to half a clock cycle. One of skill in the art will appreciate that in such a case it is difficult to find the appropriate spot on the line at which to tap the signal, i.e., the point at which the delay will exactly match halt the clock cycle.
For these and other reasons, prior art methods of providing high speed clock are not entirely satisfactory and result in design compromises and non-optimal solutions.